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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES On Chip Oscillator as clock source High Accuracy, Supports 50 Hz/60 Hz IEC 521/1036 Less than 0.1% Error Over a Dynamic Range of 500 to 1 The ADE7757 Supplies Average Real Power on the Frequency Outputs F1 and F2 The High Frequency Output CF Is Intended for Calibration and Supplies Instantaneous Real Power Direct Drive for Electromechanical Counters and Two Phase Stepper Motors (F1 and F2) Proprietary ADCs and DSP Provide High Accuracy over Large Variations in Environmental Conditions and Time On-Chip Power Supply Monitoring On-Chip Creep Protection (No Load Threshold) On-Chip Reference 2.5 V 8% (30 ppm/ C Typical) with External Overdrive Capability Single 5 V Supply, Low Power (15 mW Typical) Low Cost CMOS Process AC Input only GENERAL DESCRIPTION
Energy Metering IC with Integrated Oscillator ADE7757*
The ADE7757 specifications surpass the accuracy requirements as quoted in the IEC1036 standard. Due to the similarity between the ADE7757 and AD7755, the Application Note AN-559 can be used as a basis for a description of an IEC1036 low cost watt-hour meter reference design. The only analog circuitry used in the ADE7757 is in the sigma-delta ADCs and reference circuit. All other signal processing (e.g., multiplication and filtering) is carried out in the digital domain. This approach provides superior stability and accuracy over time and extreme environmental conditions. The ADE7757 supplies average real power information on the low frequency outputs F1 and F2. These outputs may be used to directly drive an electromechanical counter or interface with an MCU. The high frequency CF logic output, ideal for calibration purposes, provides instantaneous real power information. The ADE7757 includes a power supply monitoring circuit on the VDD supply pin. The ADE7757 will remain in reset mode until the supply voltage on VDD reaches approximately 4 V. If the supply falls below 4 V, the ADE7757 will also reset and the F1, F2 and CF outputs will be in their non-active modes. Internal phase matching circuitry ensures that the voltage and current channels are phase matched while the HPF in the current channel eliminates dc offsets. An internal noload threshold ensures that the ADE7757 does not exhibit creep when no load is present. The ADE7757 is available in 16-lead SOIC narrow-body package.
The ADE7757 is a high accuracy electrical energy measurement IC. It is a pin reduction version of AD7755 with an enhancement of a precise oscillator circuit that serves as a clock source to the chip. The ADE7757 eliminates the cost of an external crystal or resonator, thus reducing the overall cost of a meter built with this IC. The chip directly interfaces with shunt resistor and only operates with AC input.
FUNCTIONAL BLOCK DIAGRAM
VDD
AGND
DGND
ADE7757
POWER SUPPLY MONITOR V2P V2N
ADC
...110101...
MULTIPLIER
PHASE CORRECTION HPF
SIGNAL PROCESSING BLOCK
LPF
V1N
V1P
ADC
...11011001...
DIGITAL-TO-FREQUENCY CONVERTER
4kV 2.5V REFERENCE
INTERNAL OSCILLATOR
SCF
S0 S1
REFIN/OUT RCLKIN RESERVED
CF
F1
F2
*U.S. Patents 5,745,323, 5,760,617, 5,862,069, 5,872,469; other pending.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, USA. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., February 2002
PRELIMINARY TECHNICAL DATA
ADE7757-SPECIFICATIONS
Parameter ACCURACY
1, 2
(VDD = 5 V 5%, AGND = DGND = 0 V, On-Chip Reference, rCKLIN = 5 k 0.1% 5ppm/C, TMIN to TMAX = -40 C to +85 C)
Value Units Test Conditions/Comments
Measurement Error1 on Channel V1 TBD Phase Error1 Between Channels V1 Phase Lead 37 (PF = 0.8 Capacitive) V1 Phase Lag 60 (PF = 0.5 Inductive) AC Power Supply Rejection1 Output Frequency Variation (CF) DC Power Supply Rejection1 Output Frequency Variation (CF)
ANALOG INPUTS Channel V1 Maximum Signal Level Channel V2 Maximum Signal Level Input Impedance (DC) Bandwidth (-3 dB) ADC Offset Error1, 2 Frequency Output Error1 Gain Error1 REFERENCE INPUT REFIN/OUT Input Voltage Range Input Impedance Input Capacitance ON-CHIP REFERENCE Reference Error Temperature Coefficient LOGIC INPUTS3 SCF, S0, S1, Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN LOGIC OUTPUTS3 F1 and F2 Output High Voltage, VOH 4.5 Output Low Voltage, VOL 0.5 CF Output High Voltage, VOH 4 Output Low Voltage, VOL 0.5
Channel V2 with Full-Scale Signal (165 mV),+25C % Reading typ Over a Dynamic Range 500 to 1 Line Frequency = 45 Hz to 65 Hz Degrees() max Degrees() max S0 = S1 = 1, % Reading typ V1 = V2 = 100 mV rms, @50 Hz Ripple on VDD of 200 mV rms @ 100 Hz S0 = S1 = 1, % Reading typ V1 = 100 mV rms, V2 = 100 mV rms, VDD = 5 V 250 mV
mV max mV max k min kHz typ mV max % Ideal typ % Ideal typ See Analog Inputs Section V1P and V1N to AGND V2N and V2P to AGND
0.1 0.1 TBD
TBD
30 165 TBD 7 25 TBD 7
rCKLIN = 5 k 0.1% 5ppm/C rCKLIN = 5 k 0.1% 5ppm/C
See Terminology and Performance Graphs External 2.5 V Reference, V1 = 30 mV DC, V2 = 165 mV dc External 2.5 V Reference, Gain = 1 V1 = 30 mV dc, V2 = 165 mV dc 2.5 V + 8% 2.5 V - 8%
2.7 2.3 TBD 10 200 30
V max V min k min pF max mV max ppm/C typ ppm/C max
Nominal 2.5 V
2.4 0.8 3 10
V min V max A max pF max
VDD = 5 V 5% VDD = 5 V 5% Typically 10 nA, VIN = 0 V to VDD
V min V max
ISOURCE = 10 mA VDD = 5 V ISINK = 10 mA VDD = 5 V ISOURCE = 5 mA VDD = 5 V ISINK = 5 mA VDD = 5 V
V min V max
POWER SUPPLY VDD IDD
4.75 5.25
TBD
V min V max
TBD
For Specified Performance 5 V - 5% 5 V + 5%
TBD
NOTES 1 See Terminology Section for explanation of specifications. 2 See Plots in Typical Performance Graphs. 3 Sample tested during initial release and after any redesign or process change that may affect this parameter. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA ADE7757 TIMING CHARACTERISTICS1, 2
Parameter t13 t2 t3 t43, 4 t5 t6 A, B Versions 550 See Table II 1/2 t2 180 See Table III TBD
(VDD = 5 V 5%, AGND = DGND = 0 V, On-Chip Reference, rCKLIN = 5 k 0.1% 5ppm/C, TMIN to TMAX = -40 C to +85 C)
Units ms sec sec ms sec sec Test Conditions/Comments F1 and F2 Pulsewidth (Logic Low) Output Pulse Period. See Transfer Function Section Time Between F1 Falling Edge and F2 Falling Edge CF Pulsewidth (Logic High) CF Pulse Period. See Transfer Function Section Minimum Time Between F1 and F2 Pulse
NOTES 1 Sample tested during initial release and after any redesign or process change that may affect this parameter. 2 See Figure 1. 3 The pulsewidths of F1, F2 and CF are not fixed for higher output frequencies. See Frequency Outputs Section. 4 The CF pulse is always 18 s in the high frequency mode. See Frequency Outputs section and Table III. Specifications subject to change without notice.
t1
F1
.t 6 .t 2
F2
.t 3 t4 .t 5
CF
Figure 1. Timing Diagram for Frequency Outputs
ORDERING GUIDE
Model ADE7757ARN EVAL-ADE7757EB
Package Description SOIC narrow-body Evaluation Board
Package Options RN-16 Evaluation Board
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ADE7757
(TA = +25C unless otherwise noted)
PRELIMINARY TECHNICAL DATA
16-Lead Plastic SOIC, Power Dissipation . . . . . . . . . 350mW JA Thermal Impedance** . . . . . . . . . . . . . . . . . 124.9C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . +220C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. **JEDEC 1S Standard (2 layer) Board Data
ABSOLUTE MAXIMUM RATINGS*
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Analog Input Voltage to AGND V1P, V1N, V2P and V2N . . . . . . . . . . . . . . . -6 V to +6 V Reference Input Voltage to AGND . . . -0.3 V to VDD + 0.3 V Digital Input Voltage to DGND . . . . . -0.3 V to VDD + 0.3 V Digital Output Voltage to DGND . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (A, B Versions) . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150C
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADE7757 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
TERMINOLOGY
MEASUREMENT ERROR
ADC OFFSET ERROR
The error associated with the energy measurement made by the ADE7757 is defined by the following formula:
This refers to the small dc signal (offset) associated with the analog inputs to the ADCs. However, the HPF in Channel V1 eliminates the offset in the circuitry. Therefore, the power calculation is not affected by this offset.
FREQUENCY OUTPUT ERROR
%Error =
Energy registered by ADE7757 - True Energy x 100% True Energy
PHASE ERROR BETWEEN CHANNELS
The HPF (High Pass Filter) in the current channel (Channel V1) has a phase lead response. To offset this phase response and equalize the phase response between channels, a phase correction network is also placed in Channel V1. The phase correction network matches the phase to within 0.1 over a range of 45 Hz to 65 Hz and 0.2 over a range 40 Hz to 1 kHz. See Figures 19 and 20.
POWER SUPPLY REJECTION
The frequency output error of the ADE7757 is defined as the difference between the measured output frequency (minus the offset) and the ideal output frequency. The difference is expressed as a percentage of the ideal frequency. The ideal frequency is obtained from the ADE7757 transfer function--see Transfer Function section.
GAIN ERROR
This quantifies the ADE7757 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement a reading at nominal supplies (5 V) is taken. A 200 mV rms/100 Hz signal is then introduced onto the supplies and a second reading obtained under the same input signal levels. Any error introduced is expressed as a percentage of reading--see Measurement Error definition. For the dc PSR measurement a reading at nominal supplies (5 V) is taken. The supplies are then varied 5% and a second reading is obtained with the same input signal levels. Any error introduced is again expressed as a percentage of reading.
The gain error of the ADE7757 is defined as the difference between the measured output frequency (minus the offset) and the ideal output frequency. It is measured with a gain of 1 in channel V1. The difference is expressed as a percentage of the ideal frequency. The ideal frequency is obtained from the ADE7757 transfer function--see Transfer Function section.
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PRELIMINARY TECHNICAL DATA ADE7757
PIN FUNCTION DESCRIPTIONS
Pin No. 1
Mnemonic VDD
Description Power Supply. This pin provides the supply voltage for the circuitry in the ADE7757. The supply voltage should be maintained at 5 V 5% for specified operation. This pin should be decoupled with a 10 F capacitor in parallel with a ceramic 100 nF capacitor. Analog Inputs for Channel V2 (voltage channel). These inputs provide a fully differential input pair. The maximum differential input voltage is 165 mV for specified operation. The maximum signal level at these pins is 165 mV with respect to AGND. Both inputs have internal ESD protection circuitry and an overvoltage of 6 V can also be sustained on these inputs without risk of permanent damage. Analog Inputs for Channel V1 (current channel). These inputs are fully differential voltage inputs with a maximum signal level of 30 mV with respect to pin V1N for specified operation. The maximum signal level at this pin is 165 mV with respect to AGND. Both inputs have internal ESD protection circuitry and in addition an overvoltage of 6 V can be sustained on these inputs without risk of permanent damage. This provides the ground reference for the analog circuitry in the ADE7757, i.e., ADCs and reference. This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the ground reference for all analog circuitry, e.g., antialiasing filters, current and voltage sensors, etc. For accurate noise suppression, the analog ground plane should only be connected to the digital ground plane at one point. A star ground configuration will help to keep noisy digital currents away from the analog circuits. This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 2.5 V 8% and a typical temperature coefficient of 30 ppm/C. An external reference source may also be connected at this pin. In either case this pin should be decoupled to AGND with a 1 F tantalum capacitor and 100 nF ceramic capacitor. Select Calibration Frequency. This logic input is used to select the frequency on the calibration output CF. Table III shows calibration frequencies selection. These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion. With this logic input, designers have greater flexibility when designing an energy meter. See Selecting a Frequency for an Energy Meter Application. To enable the internal oscillator as a clock source to the chip, a precise 5 k resistor must be connected from this pin to DGND. Reserved pin. No load should be connected to this pin. This provides the ground reference for the digital circuitry in the ADE7757, i.e., multiplier, filters and digital-to-frequency converter. This pin should be tied to the digital ground plane of the PCB. The digital ground plane is the ground reference for all digital circuitry, e.g., counters (mechanical and digital), MCUs and indicator LEDs. For accurate noise suppression the analog ground plane should only be connected to the digital ground plane at one point only, e.g., a star ground. Calibration Frequency Logic Output. The CF logic output provides instantaneous real power information. This output is intended for calibration purposes. Also see SCF pin description. Low Frequency Logic Outputs. F1 and F2 supply average real power information. The logic outputs can be used to directly drive electromechanical counters and two phase stepper motors. See Transfer Function.
2,3
V2P, V2N
4, 5
V1N, V1P
6
AGND
7
REFIN/OUT
8 9,10
SCF S1, S0
11 12 13
RCLKIN RESERVED DGND
14 15,16
CF F2,F1
VDD
1 2 3 4 5 6 7 8
16 F1 15 F2 14 CF 13 DGND TOP VIEW 12 RESERVED (Not to Scale) 11 RCLKIN
PIN CONFIGURATION SOIC-16nb Package
V2P V2N V1N V1P AGND REFIN/OUT SCF
ADE7757
10 S0 9 S1
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PRELIMINARY TECHNICAL DATA ADE7757 -Typical Performance Characteristics
TBD
Figure 2. Error as a % Reading over Temperature on-chip reference (PF=1)
TBD
Figure 5. Error as a % of Reading over Temperature with External Reference (PF=0.5)
TBD
Figure 3. Error as a % of Reading over Temperature with on-chip reference (PF=0.5)
602k
TBD
Figure 6. Error as a %of Reading over Input Frequency
VDD 100nF VDD V2P 220V 200 150nF F1 F2 U1 ADE7757 CF V2N RESERVED 200 150nF 200 150nF S0 REFIN/OUT 1F 100nF S1 10nF 10nF 10nF SCF AGND DGND V1N V1P 5 k RCLKIN VDD 10k PS2501-1 K8 10 F
U3
K7
TBD
Figure 4. Error as a % of Reading over Temperature with External Reference (PF=1)
200 150nF 40A TO 40mA
500
Figure 7. Test Circuit for Performance Curves
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PRELIMINARY TECHNICAL DATA ADE7757
TBD
Figure 8. Channel V1 Offset Distribution
TBD
Figure 10. PSR with External Reference
TBD
Figure 9. PSR with Internal Reference
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PRELIMINARY TECHNICAL DATA ADE7757
THEORY OF OPERATION
The two ADCs digitize the voltage signals from the current and voltage sensors. These ADCs are 16-bit sigmadelta with an oversampling rate of 450 kHz. This analog input structure greatly simplifies sensor interfacing by providing a wide dynamic range for direct connection to the sensor and also simplifies the antialiasing filter design. A high pass filter in the current channel removes any dc component from the current signal. This eliminates any inaccuracies in the real power calculation due to offsets in the voltage or current signals. Because the HPF is always enabled, the IC will only operate with AC Input--see HPF and Offset Effects. The real power calculation is derived from the instantaneous power signal. The instantaneous power signal is generated by a direct multiplication of the current and voltage signals. In order to extract the real power component (i.e., the dc component), the instantaneous power signal is low-pass filtered. Figure 11 illustrates the instantaneous real power signal and shows how the real power information can be extracted by low-pass filtering the instantaneous power signal. This scheme correctly calculates real power for sinusoidal current and voltage waveforms at all power factors. All signal processing is carried out in the digital domain for superior stability over temperature and time.
DIGITAL-TOFREQUENCY LPF DIGITAL-TOFREQUENCY CF F1 F2
phase. Figure 12 displays the unity power factor condition and a DPF (Displacement Power Factor) = 0.5, i.e., current signal lagging the voltage by 60. If we assume the voltage and current waveforms are sinusoidal, the real power component of the instantaneous power signal (i.e., the dc term) is given by:
V x I x cos (60) 2
This is the correct real power calculation.
POWER INSTANTANEOUS POWER SIGNAL INSTANTANEOUS REAL POWER SIGNAL
Vx I 2
0V CURRENT VOLTAGE POWER INSTANTANEOUS POWER SIGNAL INSTANTANEOUS REAL POWER SIGNAL
TIME
VxI cos ( 60) 2 0V TIME
HPF CH1 PGA ADC MULTIPLIER CH2 ADC
VOLTAGE
60 60
CURRENT
Figure 12. DC Component of Instantaneous Power Signal Conveys Real Power Information PF < 1 Nonsinusoidal Voltage and Current
INSTANTANEOUS POWER SIGNAL- p (t)
VI VI 2 p(t) = i(t) v(t) WHERE: v(t) = V cos( t) i(t) = I cos( t) p(t) = V I {1+cos (2 t )} 2
INSTANTANEOUS REAL POWER SIGNAL
VI 2
TIME
The real power calculation method also holds true for nonsinusoidal current and voltage waveforms. All voltage and current waveforms in practical applications will have some harmonic content. Using the Fourier Transform, instantaneous voltage and current waveforms can be expressed in terms of their harmonic content.
Figure 11. Signal Processing Block Diagram
The low frequency outputs (F1, F2) of the ADE7757 is generated by accumulating this real power information. This low frequency inherently means a long accumulation time between output pulses. Consequently, the resulting output frequency is proportional to the average real power. This average real power information is then accumulated (e.g., by a counter) to generate real energy information. Conversely, due to its high output frequency and hence shorter integration time, the CF output frequency is proportional to the instantaneous real power. This is useful for system calibration, which can be done faster under steady load conditions.
Power Factor Considerations
v( t ) = V0 + 2 x Vh x sin (ht + h )
h0
(1)
where: v(t) VO Vh and h is the instantaneous voltage is the average value is the rms value of voltage harmonic h is the phase angle of the voltage harmonic.
i( t ) = I 0 + 2 x I h x sin (ht + h )
h 0
(2)
where: i(t) IO Ih and h is the instantaneous current is the dc component is the rms value of current harmonic h is the phase angle of the current harmonic. REV. PrC.
The method used to extract the real power information from the instantaneous power signal (i.e., by low-pass filtering) is still valid even when the voltage and current signals are not in -8-
PRELIMINARY TECHNICAL DATA ADE7757
Using Equations 1 and 2, the real power P can be expressed in terms of its fundamental real power (P1) and harmonic real power (PH).
Channel V2 (Voltage Channel )
P = P1 + PH
where:
The output of the line voltage sensor is connected to the ADE7757 at this analog input. Channel V2 is a fully differential voltage input with maximum peak differential signal of 165 mV. Figure 14 illustrates the maximum signal levels that can be connected to the ADE7757 Channel V2.
V2
P1 = V1 x I1 cos 1 1 = 1 - 1
and
+165mV
(3)
VCM DIFFERENTIAL INPUT 165mV MAX PEAK COMMON-MODE 25mV MAX -165mV V2 VCM
V2P V2N
AGND
PH =
V
h 1
h
x I h cos h
(4)
Figure 14. Maximum Signal Levels, Channel V2
h = h - h
As can be seen from Equation 4 above, a harmonic real power component is generated for every harmonic, provided that harmonic is present in both the voltage and current waveforms. The power factor calculation has previously been shown to be accurate in the case of a pure sinusoid, therefore the harmonic real power must also correctly account for power factor since it is made up of a series of pure sinusoids. Note that the input bandwidth of the analog inputs is 14 kHz with.
ANALOG INPUTS Channel V1 (Current Channel )
Channel V2 is usually driven from a common-mode voltage, i.e., the differential voltage signal on the input is referenced to a common mode (usually AGND). The analog inputs of the ADE7757 can be driven with common-mode voltages of up to 25 mV with respect to AGND. However best results are achieved using a common mode equal to AGND.
Typical Connection Diagrams
Figure 15 shows a typical connection diagram for Channel V1. A shunt is the current sensor selected for this example because of its low cost compared to other current sensors such as the CT (current transformer). This IC is ideal for low current meters.
Rf 30mV Cf V1P V1N
SHUNT
The voltage output from the current sensor is connected to the ADE7757 here. Channel V1 is a fully differential voltage input. V1P is the positive input with respect to V1N. The maximum peak differential signal on Channel V1 should be less than 30 mV (21 mV rms for a pure sinusoidal signal) for specified operation.
V1 +30mV V1P DIFFERENTIAL INPUT 30mV MAX PEAK VCM COMMON-MODE 6.25mV MAX -30mV VCM V1 V1N
AGND PHASE NEUTRAL
Rf
Cf
Figure 15. Typical Connection for Channel V1
Figure 16 shows a typical connection for Channel V2. Typically, ADE7757 is biased around the neutral wire, and a resistor divider is used to provide a voltage signal that is proportional to the line voltage. Adjusting the ratio of Ra, Rb and VR is also a convenient way of carrying out a gain calibration on a meter.
Ra* Rb* VR* Cf
AGND
165mV Rf
V2P V2N Cf
Figure 13. Maximum Signal Levels, Channel V1
PHASE
NEUTRAL
The diagram in Figure 13 illustrates the maximum signal levels on V1P and V1N. The maximum differential voltage is 30 mV. The differential voltage signal on the inputs must be referenced to a common mode, e.g. AGND. The maximum common mode signal is 6.25 mV as shown in Figure 13.
* Ra >> Rf + VR * Rb + VR = Rf
Figure 16. Typical Connections for Channel V2
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PRELIMINARY TECHNICAL DATA ADE7757
POWER SUPPLY MONITOR
The ADE7757 contains an on-chip power supply monitor. The power supply (VDD) is continuously monitored by the ADE7757. If the supply is less than 4 V, the ADE7757 will reset. This is useful to ensure proper device operation at power-up and power-down. The power supply monitor has built in hysteresis and filtering that provide a high degree of immunity to false triggering from noisy supplies. As can be seen from Figure 17, the trigger level is nally set at 4 V. The tolerance on this trigger level within 5%. The power supply and decoupling for part should be such that the ripple at VDD does not 5 V 5% as specified for normal operation.
VDD 5V 4V
Vos x I os Vx I 2
DC COMPONENT (INCLUDING ERROR TERM) IS EXTRACTED BY THE LPF FOR REAL POWER CALCULATION
I os x V Vos x I 0 FREQUENCY - Rad/s
nomiis the exceed
Figure 18. Effect of Channel Offset on the Real Power Calculation
The HPF in Channel V1 has an associated phase response that is compensated for on-chip. Figures 19 and 20 show the phase error between channels with the compensation network activated. The ADE7757 is phase compensated up to 1 kHz as shown. This will ensure correct active harmonic power calculation even at low power factors.
0.30
TIME
0V
0.25
INTERNAL ACTIVATION
0.20
INACTIVE ACTIVE INACTIVE
PHASE - Degrees
0.15 0.10 0.05 0 -0.05 -0.10
Figure 17. On-Chip Power Supply Monitor HPF and Offset Effects
Figure 18 illustrates the effect of offsets on the real power calculation. As can be seen, offsets on Channel V1 and Channel V2 will contribute a dc component after multiplication. Since this dc component is extracted by the LPF and used to generate the real power information, the offsets will contribute a constant error to the real power calculation. This problem is easily avoided by the built-in HPF in Channel V1. By removing the offsets from at least one channel, no error component can be generated at dc by the multiplication. Error terms at the line frequency () are removed by the LPF and the digital-tofrequency conversion--see Digital-to-Frequency Con verConversion. The equation below shows how power calculation is affected by the dc offsets in the current and voltage channels:
0
100
200
300
400 500 600 FREQUENCY - Hz
700
800
900 1000
Figure 19. Phase Error Between Channels (0 Hz to 1 kHz)
0.30 0.25 0.20
PHASE - Degrees
0.15 0.10 0.05 0 -0.05 -0.10 40 45 50 55 60 FREQUENCY - Hz 65 70
{Vcos(t) + Vos }x {I cos(t ) + I os } =
VxI + Vos x I os + Vos x I cos(t ) + I os x V cos(t ) 2 VxI + x cos( 2t ) 2
Figure 20. Phase Error Between Channels (40 Hz to 70 Hz)
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PRELIMINARY TECHNICAL DATA ADE7757
DIGITAL-TO-FREQUENCY CONVERSION
As previously described, the digital output of the low-pass filter after multiplication contains the real power information. However, since this LPF is not an ideal "brick wall" filter implementation, the output signal also contains attenuated components at the line frequency and its harmonics, i.e., cos(ht) where h = 1, 2, 3, . . . etc. The magnitude response of the filter is given by:
H( f ) = 1+
1 f2 8.9 2
(5)
ing it to a frequency. This shorter accumulation period means less averaging of the cos (2t) component. Consequently, some of this instantaneous power signal passes through the digital-to-frequency conversion. This will not be a problem in the application. Where CF is used for calibration purposes, the frequency should be averaged by the frequency counter which will remove any ripple. If CF is being used to measure energy; for example, in a microprocessor-based application, the CF output should also be averaged to calculate power. Because the outputs F1 and F2 operate at a much lower frequency, a lot more averaging of the instantaneous real power signal is carried out. The result is a greatly attenuated sinusoidal content and a virtually ripple-free frequency output.
Interfacing the ADE7757 to a Microcontroller for Energy Measurement
For a line frequency of 50 Hz this would give an attenuation of the 2 (100 Hz) component of approximately - 22 dB. The dominating harmonic will be at twice the line frequency (2) due to the instantaneous power calculation. Figure 21 shows the instantaneous real power signal at the output of the LPF which still contains a significant amount of instantaneous power information, i.e., cos (2t). This signal is then passed to the digital-to-frequency converter where it is integrated (accumulated) over time in order to produce an output frequency. The accumulation of the signal will suppress or average out any non-dc components in the instantaneous real power signal. The average value of a sinusoidal signal is zero. Hence the frequency generated by the ADE7757 is proportional to the average real power. Figure 21 shows the digital-to-frequency conversion for steady load conditions, i.e., constant voltage and current.
The easiest way to interface the ADE7757 to a microcontroller is to use the CF high frequency output with the output frequency scaling set to 2048 x F1, F2. This is done by setting SCF = 0 and S0 = S1 = 1, see Table III. With full-scale ac signals on the analog inputs, the output frequency on CF will be approximately 2.867 kHz. Figure 22 illustrates one scheme which could be used to digitize the output frequency and carry out the necessary averaging mentioned in the previous section.
CF
FREQUENCY RIPPLE AVERAGE FREQUENCY
10%
F1 DIGITAL-TOFREQUENCY V MULTIPLIER I LPF TO EXTRACT REAL POWER (DC TERM) Vx I 2 LPF DIGITAL-TOFREQUENCY CF F1 F2
FREQUENCY
TIME
TIME CF
MCU
ADE7757
CF
COUNTER
FREQUENCY
TIME cos ( 2 t ) ATTENUATED BY LPF
TIMER
0
2 FREQUENCY (RAD/S)
Figure 22. Interfacing the ADE7757 to an MCU
INSTANTANEOUS REAL POWER SIGNAL (FREQUENCY DOMAIN)
Figure 21. Real Power-to-Frequency Conversion
As shown, the frequency output CF is connected to an MCU counter or port. This will count the number of pulses in a given integration time which is determined by an MCU internal timer. The average power is proportional to the average frequency is given by:
As can be seen in the diagram, the frequency output CF is seen to vary over time, even under steady load conditions. This frequency variation is primarily due to the cos (2t) component in the instantaneous real power signal. The output frequency on CF can be up to 2048 times higher than the frequency on F1 and F2. This higher output frequency is generated by accumulating the instantaneous real power signal over a much shorter time while convertREV. PrC.
Average Frequency = Average Power =
Counter Time
The energy consumed during an integration period is given by:
Energy = Average Power x Time =
Counter x Time = Counter Time
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PRELIMINARY TECHNICAL DATA ADE7757
For the purpose of calibration, this integration time could be 10 to 20 seconds in order to accumulate enough pulses to ensure correct averaging of the frequency. In normal operation the integration time could be reduced to one or two seconds depending, for example, on the required update rate of a display. With shorter integration times on the MCU the amount of energy in each update may still have some small amount of ripple, even under steady load conditions. However, over a minute or more the measured energy will have no ripple.
Power Measurement Considerations Table I. F1-4 Frequency Selection
S1 0 0 1 1
S0 0 1 0 1
F1-4 (Hz) 0.85 1.7 3.4 6.8
NOTE *F1-4 is a binary fraction of the internal oscillator frequency
Example
Calculating and displaying power information will always have some associated ripple that will depend on the integration period used in the MCU to determine average power and also the load. For example, at light loads the output frequency may be 10 Hz. With an integration period of two seconds, only about 20 pulses will be counted. The possibility of missing one pulse always exists as the ADE7757 output frequency is running asynchronously to the MCU timer. This would result in a one-in-twenty or 5% error in the power measurement.
TRANSFER FUNCTION Frequency Outputs F1 and F2
In this example, with ac voltages of 30 mV peak applied to V1 and 165 mV peak applied to V2, the expected output frequency is calculated as follows:
F1- 4 V1rms
= 0.85 Hz, S0 = S1 = 0 = 0.03/ = 0.165/
2
volts
2
V 2 rms
volts
Vref
= 2.5 V (nominal reference value). NOTE: If the on-chip reference is used, actual output frequencies may vary from device to device due to reference tolerance of 8%.
The ADE7757 calculates the product of two voltage signals (on Channel V1 and Channel V2) and then low-pass filters this product to extract real power information. This real power information is then converted to a frequency. The frequency information is output on F1 and F2 in the form of active low pulses. The pulse rate at these outputs is relatively low, e.g., 0.175 Hz maximum for ac signals with S0 = S1 = 0--see Table II. This means that the frequency at these outputs is generated from real power information accumulated over a relatively long period of time. The result is an output frequency that is proportional to the average real power. The averaging of the real power signal is implicit to the digital-to-frequency conversion. The output frequency or pulse rate is related to the input voltage signals by the following equation:
Freq =
515 .85 x 0 .03 x 0 .165 x 0 .85 2 x 2 x 2 .5 2
= 0 .175
Table II. Maximum Output Frequency on F1 and F2
S1 0 0 1 1
S0 0 1 0 1
Max Frequency for AC Inputs (Hz) 0.175 0.35 0.7 1.4
Freq =
where:
515.84 x V 1rms x V 2 rms x F1- 4 Vref 2
Frequency Output CF
Freq = Output frequency on F1 and F2 (Hz)
V1rms = Differential rms voltage signal on Channel V1 (volts)
V 2 rms = Differential rms voltage signal on Channel V2
(volts)
Vref
F1- 4
= The reference voltage (2.5 V 8%) (volts) = One of four possible frequencies selected by using the logic inputs S0 and S1--see Table I.
The pulse output CF (Calibration Frequency) is intended for calibration purposes. The output pulse rate on CF can be up to 2048 times the pulse rate on F1 and F2. The lower the F1-4 frequency selected, the higher the CF scaling (except for the high frequency mode SCF = 0, S1 = S0 = 1). Table III shows how the two frequencies are related, depending on the states of the logic inputs S0, S1 and SCF. Due to its relatively high pulse rate, the frequency at CF logic output is proportional to the instantaneous real power. As with F1 and F2, CF is derived from the output of the low-pass filter after multiplication. However, because the output frequency is high, this real power information is accumulated over a much shorter time. Hence less averaging is carried out in the digital-to-frequency conversion. With much less averaging of the real power signal, the CF output is much more responsive to power fluctuations--see Signal Processing Block in Figure 11.
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PRELIMINARY TECHNICAL DATA ADE7757
Table III. Maximum Output Frequency on CF
SCF 1 0 1 0 1 0 1 0
S1 0 0 0 0 1 1 1 1
S0 CF Max for AC Signals (Hz) 0 0 1 1 0 0 1 1 128 x F1, F2 = 22.4 64 x F1, F2 = 11.2 64 x F1, F2 = 22.4 32 x F1, F2 = 11.2 32 x F1, F2 = 22.4 16 x F1, F2 = 11.2 16 x F1, F2 = 22.4 2048 x F1, F2 = 2.867 kHz
Column 4 of Table V. The closest frequency in Table V will determine the best choice of frequency (F1-4). For example, if a meter with a maximum current of 25 A is being designed, the output frequency on F1 and F2 with a meter constant of 100 imp/kWhr is 0.153 Hz at 25 A and 220 V (from Table IV). Looking at Table V, the closest frequency to 0.153 Hz in column four is 0.175 Hz. Therefore F3 (3.4 Hz--see Table I) is selected for this design.
Frequency Outputs
SELECTING A FREQUENCY FOR AN ENERGY METER APPLICATION
As shown in Table I, the user can select one of four frequencies. This frequency selection determines the maximum frequency on F1 and F2. These outputs are intended for driving an energy register (electromechanical or others). Since only four different output frequencies can be selected, the available frequency selection has been optimized for a meter constant of 100 imp/kWhr with a maximum current of between 10 A and 120 A. Table IV shows the output frequency for several maximum currents (IMAX) with a line voltage of 220 V. In all cases the meter constant is 100 imp/kWhr.
Table IV. F1 and F2 Frequency at 100 imp/kWhr
Figure 1 shows a timing diagram for the various frequency outputs. The outputs F1 and F2 are the low frequency outputs that can be used to directly drive a stepper motor or electromechanical impulse counter. The F1 and F2 outputs provide two alternating low frequency pulses. The pulsewidth (t1) is set such that if F1 and F2 falls below 1100 ms (0.909 Hz) the pulsewidth of F1 and F2 is set to half of their period. The maximum output frequencies for F1 and F2 are shown in Table II. The high frequency CF output is intended to be used for communications and calibration purposes. CF produces a 180 ms-wide active high pulse (t4) at a frequency proportional to active power. The CF output frequencies are given in Table III. As in the case of F1 and F2, if the period of CF (t5) falls below 360 ms, the CF pulsewidth is set to half the period. For example, if the CF frequency is 20 Hz, the CF pulsewidth is 25 ms. NOTE: When the high frequency mode is selected, (i.e., SCF = 0, S1 = S0 = 1) the CF pulsewidth is fixed at 36 s. Therefore t4 will always be 36 s, regardless of output frequency on CF.
NO LOAD THRESHOLD
I MAX 12.5 A 25.0 A 40.0 A 60.0 A 80.0 A 120.0 A
F1 and F2 (Hz) 0.076 0.153 0.244 0.367 0.489 0.733
The F1-4 frequencies allow complete coverage of this range of output frequencies (F1, F2). When designing an energy meter the nominal design voltage on Channel V2 (voltage) should be set to half-scale to allow for calibration of the meter constant. The current channel should also be no more than half-scale when the meter sees maximum load. This will allow over current signals and signals with high crest factors to be accommodated. Table V shows the output frequency on F1 and F2 when both analog inputs are half-scale. The frequencies listed in Table V align very well with those listed in Table IV for maximum load.
Table V. F1 and F2 Frequency with Half-Scale AC Inputs
S1 0 0 1 1
S0 0 1 0 1
F1-4 0.85 1.7 3.4 6.8
Frequency on F1 and F2- CH1 and CH2 Half-Scale AC Inputs 0.0438 Hz 0.0875 Hz 0.175 Hz 0.35 Hz
The ADE7757 also includes a "no load threshold" and "startup current" feature that will eliminate any creep effects in the meter. The ADE7757 is designed to issue a minimum output frequency. Any load generating a frequency lower than this minimum frequency will not cause a pulse to be issued on F1, F2 or CF. The minimum output frequency is given as 0.0014% of the full-scale output frequency for each of the F1-4 frequency selections--see Table I. For example, an energy meter with a meter constant of 100 imp/kWhr on F1, F2 using F3 (3.4 Hz), the minimum output frequency at F1 or F2 would be 0.0014% of 3.4 Hz or 4.76 x 10-5 Hz. This would be 3.05 x 10-3 Hz at CF (64 x F1 Hz) when SCF = S0 = 1, S1 = 0. In this example the no load threshold would be equivalent to 1.7 W of load or a startup current of 8 mA at 220 V. Comparing this value to the IEC1036 specification which states that the meter must start up with a load equal to or less than 0.4% Ib. For a 5A (Ib) meter 0.4% of Ib is equivalent to 20 mA.
When selecting a suitable F1-4 frequency for a meter design, the frequency output at IMAX (maximum load) with a meter constant of 100 imp/kWhr should be compared with REV. PrC. -13-
PRELIMINARY TECHNICAL DATA ADE7757
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead SOIC narrow-body
0.3937 (10.00) 0.3859 (9.80) 0.1574 (4.00) 0.1497 (3.80)
16 1 9 8
0.2440 (6.20) 0.2284 (5.80)
PIN 1
0.050 (1.27) BSC
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
0.0098 (0.25) 0.0040 (0.10)
0.0192 (0.49) 0.0138 (0.35)
8 SEATING 0.0099 (0.25) 0 0.0500 (1.27) PLANE 0.0160 (0.41) 0.0075 (0.19)
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